1. Field of the Invention
The present invention relates to a delay circuit for delaying an input signal by a quarter of a cycle, i.e., 90 degrees in phase, to output a delayed signal in a signal processing circuit, e.g., a receiving circuit for radio signals and a processing circuit of a computer (such a delay circuit is referred to as "90-degree phase shifter" in the present invention).
2. Description of the Background Art
FIG. 14 is a timing chart showing a relation between the data S6 and clock S1 which changes in the same cycle with the same phase as the data S6 does. In such a signal processing circuit which receives the data S6 and the clock S1, the data S6 can not be appropriately latched by using the change on rise or fall of the clock S1 since the data S6 changes as the clock S1 changes. For this reason, it is necessary to shift the clock S1 in phase relative to the data S6.
FIG. 15 is a timing chart after shifting the change of the clock S1 relative to that of the data S6 by 90 degrees in phase. By this, the rise or fall of the clock S1 comes at the center of an eye pattern of the data S6 (the halfway point of adjacent changes of the data 6), and therefore the data S6 can be most surely latched by using the change of the clock S1.
FIG. 16 is a circuit diagram showing an outline of an input interface of a chip 91 which receives the data S6 and the clock S1. The data S6 and the clock S1 are propagated through transmission lines 110a and 110b outside the chip 91 to pad electrodes 111a and 111b inside the chip 91 and buffered by buffers 112a and 112b, respectively. A phase shifter 200 thereafter shifts the clock S1 by 90 degrees, to generate a clock S2.
Latch circuits 113a and 113b each have a data input end D receiving the buffered data S6 and a clock input end T receiving the clock S2. The latch circuit 113a latches the data S6 on the rise of the clock S2 and the latch circuit 113b latches the data S6 on the fall of the clock S2.
FIG. 17 is a circuit diagram illustrating a configuration of the 90-degree phase shifter 200. The 90-degree phase shifter 200 comprises a PLL (Phase-Locked Loop) circuit 120 and a delay stage 5. The PLL circuit 120 comprises a VCO circuit 122, a phase comparator 121 and a low-pass filter 2. The PLL circuit 120 generates a signal S9 locked on a reference signal S7 in phase. At this time, the delay stage 5 uses a delay adjustment signal S4 given by the low-pass filter 2 for delay adjustment and delays the clock S1 buffered by the buffer 112b by 90 degrees to output the output clock S2.
In the 90-degree phase shifter 200, the number of buffers 4 in the VCO circuit 122 and the delay adjustment signal S4 from the low-pass filter 2 are determined so that a delay in the VCO circuit 122 may be a half of the cycle of the reference signal S7 (180 degrees in phase) when the PLL circuit 120 is locked. A pair of outputs from the last-stage buffer 4 are inverted in polarity and connected to a pair of inputs of the first-stage buffer 4. The VCO circuit 122 can thereby stably oscillate when given the reference signal S7 and obtains the signal S9 locked in the same cycle with the same phase as the reference signal S7.
Then, when the clock S1 is used as the reference signal S7 and the delay stage 5 is provided with buffers 4 half as much as the internal buffers 4 constituting the VCO circuit 122, the 90-degree phase shifter 200 can generate the signal S2 with its cycle shifted by a quarter relative to the clock S1. In other words, the delay stage 5 keeps a 90-degree delay in phase, not depending on the process or other conditions, so far as the PLL circuit 120 is locked.
The PLL circuit, however, has problems of instability and more volume of hardware and more power consumption due to necessity for the VCO circuit in general.
To solve the above problems suggested is a technique for shifting phase by 90 degrees without the PLL circuit 120. FIG. 18 is a circuit diagram illustrating a constitution of a 90-degree phase shifter 201 used instead of the 90-degree phase shifter 200 of FIG. 16. The 90-degree phase shifter 201 has a constitution where the VCO circuit 122 is omitted and the phase comparator 121 is replaced by a phase detection circuit 100 in the 90-degree phase shifter 200. In short, the 90-degree phase shifter 201 is a DLL (Delay-Locked Loop) circuit.
FIG. 19 is a circuit diagram illustrating a configuration of the 90-degree phase detection circuit 100. The 90-degree phase detection circuit 100 comprises an EXOR circuit 10a and a charging pump circuit 11. Exclusive OR of the clocks S1 and S2 obtained by the EXOR circuit 10a is converted into a UP/DOWN signal S3 in a form of current. To supply the UP/DOWN signal S3, the charging pump circuit 11 is provided with current sources whose current amounts depend on bias signals.
The UP/DOWN signal S3 is given to a low-pass filter 2 where its current amount is integrated and converted into a DC voltage signal as the delay adjustment signal S4 to be transferred to the delay stage 5. The delay adjustment signal S4 makes a feed-back to cause a delay for obtaining the clock S2 from the clock S1.
In the EXOR circuit 10a, however, the clock S1 is transferred to the charging pump circuit 11 through a transfer gate or a NOT circuit while the clock S2 is applied only to a gate for controlling ON/OFF of the transfer gate. Thus, the clocks S1 and S2 receive different input loads in the EXOR circuit 10a. Therefore, there arises a problem of phase shift of the clock S2, where the clock S2 is balanced being further shifted from the 90-degree-shifted phase relative to the clock S1 (this phase shift is referred to as "phase offset" hereinafter).
A suggestion to solve this problem is to use an EXOR circuit 10b having a configuration shown in FIG. 20 instead of the EXOR circuit 10a. Though this configuration gives the same input load to the clocks S1 and S2, it requires more transistors for a compound gate and therefore causes another problem of enlargement in circuit scale.